    
Kmt36264
Junior Member
Username: Kmt36264
Post Number: 28
Registered: 1-2006
| | Posted on Thursday, May 11, 2006 - 12:34 am: | 
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I got this from someone else. I can't remember his name or handle to give credit. I tuned up two of these and was able to get them to key 4 and swing 8. Out of the box, they didn't have any forward modulation at all. Be careful not to turn the modulation up too much or you will get a pumping effect when the limiter kicks in. You will notice a much better receive after tune-up also.
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Midland 1000
7. THEORY OF OPERATIONS
7.1 PLL
See Frequency Synthesizer Block Diagram and Schematic.
4. Introduction
The Synthesizer is implemented with the following
Components: PLL IC (IC1)
X-TAL (X1)
Varicap Diode (D601)
Transistor (Q601, Q602, Q603, Q502, Q503)
LED Display
IC3 is a CMOS LSI that includes most of the PLL block.
The VCO with Varicap Diode D601 as part of the oscillator tank circuit.
Q602 is a switching transistor to connect or disconnect the tuning capacitor in the VCO oscillator tank circuit for transmitter or receiver.
2. Reference Frequency
The crystal X1 (10.240 MHz) and other component at pins 19 and 20 of IC3.From an oscillator with an amplifier internal to IC3.The oscillator output is internally fed to a divide by 4096 to produce a 2.5kHz. Square wave, which is the reference input to the phase detector.
3. VCO
Q603 is connected as a Harley type oscillator with Varicap diode as part of the tank circuit. With appropriate control voltage on D601 the VCO can be made to oscillate over the required rang of 13.4825 MHz to 16.710 MHz.
4. Programmable Divider and its Control
The programmable inputs (7-segment code) are fed to pins 1 to 7 IC3 the programmable inputs consist a 7segment code to light channel indicator LED Display For CH.1 B and C of the first LED element of LED will light.
The programmable input B goes low to produce CH. 1 devisor (RX : N=6508, TX : 5393). For each channel number input, an internal code converter ROM provides the appropriate binary control to the programmable divider for channel. Since the binary number required is different during transmit and receive, an additional bit is required at pin 20 of IC3 to allow the ROM to recognize the TX/RX status. The programmable divider output is fed to the phase detector for comparison with the 2.5KHz reference.
5. phase Detectors and VCO Control
The phase detector is a digital phase comparator which compares the leading edges of the reference with programmable divider output square waves and develops a series of pulses whose DC level depends on whether the phase error is leading or lagging. The phase detector pulse output is fed to a charge pump and then to base of Q502. The charge pump output is fed to an active low pass filter, which consist of R508, R513 C504 and the amplifier Q502, Q503. The low pass filter output at pin 27 of IC3 is further filtered and fed to Varicap D601 to control the VCO frequency. The result is a second order PLL with the loop dynamics essentially controlled by the active
low pass filter.
6. Transmit/ Receive, Buffer AMP.
The VCO output is fed into buffer AMP Q601 from secondary of L4
7. Transmit Doubler
The Q601 output obtained as base output and fed to the base of double transistor Q11. At this stage, the frequency is doubled. The Q11 output tank circuit is double tuning circuit (27MHz) L5 and L6 to stop the 13.5Mhz, frequency.
8. Switching of Tuning Capacitor in VCO Oscillator Tank Circuit
The VCO circuit must tune with a wide rang of frequencies 13.4825MHz~13.7025MHz for transmitter and 16.27MHz~16.710MHz for receiver. The use for one tuning capacitor in common has such adverse effect and decreases in the tuning circuit and the occurrence of many spuriouses. To eliminate these effects, the tuning capacitance is switched for transmission or reception. The tank circuit consists of the primary of L4, C605 and C606 when receiving, Q602 becomes off so, the primary of L4 and make tuning function when transmitting, Q602 becomes on. So, the primary of L4 and the parallel capacitance of C606 and C609 make tuning function.
9. Receiver Local Oscillator Outputs
First Mixer:
The secondary output of VCO tank circuit L4 is injected through buffer AMP Q601 and the buffer CKT output through the base of 1st mixer.
Second Mixer:
The oscillation output, oscillated with 10.240MHz crystals X1 across pins 19 and 20 of IC3, is output from pin 19 and injected into the base of Q103.
10. Fault Protection
IC3 includes an auxiliary exclusive or phase detector which functions as lock detector. If lock is lost pin 18 goes low and the base bias of Q12 is cut off, to prohibit transmission and reception. Transmission cannot be made if a code other than those for 40 channel is input is IC3.
11. Frequency Stability
LET : FO = Crystal Oscillator Frequency
FR = Phase Detector Reference Frequency
FVCO = VCO Frequency
FT = Transmit Frequency
THEN = FR = FO/4096
And under locked conditions :
FR = FVCO/N Where N is the programmable divider divide ratio
THEN : FVCO = N X FR = N (FO/4096)
From which it can be seen that the percentage error in FT is the same as the percentage error in FO.
The stability of the crystal oscillator is determined primarily by the crystal and to a lesser extent by the active and passive components of the oscillator. The choice of crystal and components is such that the required frequency stability is maintained over the required voltage and temperature range.
7.2. Transmitter
1. RF Amplification
The output of double AMP Q11 is fed through double tuning (27MHz) L5 and L6 to the base of PRE AMP. The output is then supplied through tuning circuit C11 to RF driver AMP Q13 output is capacitance divided by tuning circuit C86 and C88 and passed through the base of final RF stage the Q14 output is supplied to the antenna through L-C tuning circuit.
2.Circuit For Suppression Of Spurious Radiation
The tuning circuit between frequency synthesizer and final AMP Q14 and LPF(Low Pass Filter) Module in the Q14 output circuit sever to suppress spurious radiation. This Module serves to impedance match Q14 to the antenna and to reduce spurious content to acceptable levels In the frequency synthesizer.
3.circuits For Limiting Power
During factory alignment, the series base resistor of final Q14 (R70) is selected to limit the available power to slightly more than 4 watts. The tuning is adjusted so that the actual power is from 3.6 to 4.4 watts there are no other controls for adjusting power.
4.Modulation
The MIC input is fed to audio power IC2 which feeds modulation transformer T1. The audio output at the secondary of T1 is fed in series with the B+ voltage the diode D9to the collectors of driver Q13 and final Q14 to collector modulate both these stages.
5.Circuits For Limiting Modulation
A portion of the modulating voltage is rectified by D9 which turns on Q9 which attenuates the MIC input to MIC AMP IC2 the resulting feedback loop-keeps the modulation from exceeding 100% inputs approximately 40dB greater than that required to produce 50% modulation. The attack time is about 50ms and the release time is about 300ms
7.3.Receiver
The receiver is a double conversion super heterodyne with the first IF at 10.695MHz and the second IF at 455KHz. The synthesizer supplies the first local oscillator 10.695MHz below the received frequency and the second local oscillator at 10.240MHz. Squelch is controlled by Q10.
Q102 is a 27MHz input amplifier, and any excessive input signal is limited by diodes
D101 The amplified 27MHz is mixed with VCO frequency selected by channel switch.
For CH.1 VCO is set at 16.27 MHz. The resulting first IF is 26.965-
16.27 = 10.695MHz
Q103 is the first converter, and the 10.695 MHz is sharply filtered by L104 and a ceramic filter CF1. The first IF is again mixed with a second local oscillator of 10.24 MHz
10.695-10.24 = 0.455MHz.
Q201 is the second converter. Second IF is filtered by a razor sharp ceramic filter of CF2 coupled wit Q202, L3
Q202 is the first 455KHz amplifiers, and the Q203 being the last amplifier.
D201 is a detector diode, which produces audio. The negative voltage also provides forward biasing to the Cathode of ANL clipping TR of Q 204. The biasing voltage has a time constant determined by R217 and C209. There for any sharp negative going pulse from D201, will back bias Q204 and be clipped.
SQ is controlled by Q10
8.ALIGNMENT INSTRUCTIONS
Warning : Any repairs or adjustment should be made under the supervision of a qualified radio-telephone technician.
8.1. VCO
a. Connect the power supply (DC 13.8V)
b. Connect the oscilloscope probe to test point
c. Adjust the coil L4 for 2V at 1-Ch RX.
d. Check that CH-40 voltmeter of receiver reads from 2 to 4 volts.
8.2 Transmitter
a. TX Power alignments
With RF voltmeter at base of Q11, transmit of channel 19. Adjust in turn L5, L6. For maximum reading on RF voltmeter. Repeat as needed. Remove RF voltmeter.
b. Max Mod Alignments
Adjust RV2 to obtain 90% MOD. At 20dB greater than 50% MOD. AF 1KHz.
c. Power Meter Alignments
1. Connect RF voltmeter and dummy load to antenna connector.
2. Push PTT switch and reduce supply voltmeter until read 3.6 watt from RF voltmeter output.
3. Adjust RV4 until P-4 (LED) just appeared.
d. Final Check
1. Output power should be from 3.6 to 4.4 watts.
2. Frequency should be within +400Hz of channel center frequency.
3. Spurious content as observed on spectrum synthesizer should be at least 60dB below carrier.
4. With 2500Hz modulation at 20dB greater than that required to produce 50% Modulation, occupied bandwidth should be at least 2 dB better than limit spec.
8.3 RX
Sensitivity Alignment
a. Set the signal generator to provide 27.185MHz, 1KHz 30% modulation. Place the channel selector in channel 19 position.
Adjust L1, L102, L104, L2 and L3 for maximum audio output across the 8ohms dummy load resistor. This alignment should be performed by gradually decreasing the signal output signal to a minimum level required for tuning to avoid in accurate alignment due to AGC action.
S-Meter Alignment
a. Set the signal generator to provide 67dBm, 1KHz, 30% modulation antenna input.
b. Adjust RV3 until S-9 (LED) Just appeared.
Squelch Circuit Alignment
a. Set the signal generator to provide 60dB, 1KHz 30% mod antenna input.
b. Rotate the squelch control in full clockwise direction.
c. Temporarily adjust RV1 for maximum audio out put, and note the audio output level. Then adjust RV1 so that audio output just appeared.
d. Next, reduce the antenna input signal level to 53~58dB and make sure the audio output decreases to zero.
e. Reduce antenna signal input level to zero, and adjust the SQ control until. The noise output decreases to just disappear.
9. SEMICONDUCTORS AND FUNCTIONS
IC
Function
Ref. No. Description RX TX Manufacturer
IC1 C5121 PLL IC PLL IC NPC
IC2 KIA7217AP Audio Amp Audio Amp K.E.C.
IC301 DBL1061 LED driver LED driver DAEWOO
TR
Function
Ref. No. Description RX TX Manufacturer
Q1 KTC3880S AGC - K.E.C.
Q10 KTC3875S CONTROL Sq - K.E.C.
Q102 KTC3880S RF Amp - K.E.C.
Q103 KTC3880S 1ST Mixer - K.E.C.
Q11 KTC3880S - Doubler K.E.C.
Q12 KTC3880S - Pre Amp K.E.C.
Q13 KTC1006 - RF Driver K.E.C.
Q14 KTC2078 - RF Power K.E.C.
Q2 KTA1504 Digit Switching Digit Switching K.E.C.
Q201 KTC3880S 2nd Mixer - K.E.C.
Q202 KTC3880S IF Amp - K.E.C.
Q203 KTC3880S IF amp - K.E.C.
Q204 KTA1504Y ANL Clipping - K.E.C.
Q3 KTA1504 Digit Switching Digit Switching K.E.C.
Q4 KTA1504 Digit Switching Digit Switching K.E.C.
Q5 KTC3875S Regulator Regulator K.E.C.
Q6 KTA1504 - TX B+ Switching K.E.C.
Q601 KTC3880S Buffer Buffer K.E.C.
Q602 KTC3875S - TX VCO Switching K.E.C.
Q603 KTC3880S VCO VCO K.E.C.
Q9 KTA1504S - ALC TR. K.E.C. |
